The 2nd last day of 1 Gbps debugging
Today it came to light that complete simulation environment cannot be built as parts of the code actually probe PHY status registers. So the idea of top level design testbench did n't work. So i am back to unit testing and making sure that there is nothing in the code that is responsible for generating conditions that make a packet drop from MAC. After that i shall send traffic from FPGA to PC and see if the receiver PC's MAC is able to catch up or not by doing ifconfig or other utilities that can help detect packet loss. It seems likely that receiver MAC is not able to keep up.
This whole saga should end tomorrow. I am pretty hopeful.
Other than that we celebrated our holy Eid today. So spending some time with the family is good. It is good to take a break from GSoC.