Week 2 summary: forming physical specifications
Serial expansion board status:
- Decided to keep RJ45, DB9 and DIN8 connectors. RJ45 will be for RS422/485 only. If anyone needs RS232 over RJ45 they may use a DB9 to RJ45 converter cable. The board would get complicated if an option for giving both RS232 and RS485 through RJ-45 has to be provided.
- I will be using separate line-drivers for RS232 and RS485, no SP33x. This gives user an option to populate the components depending on what their camera supports
- To ensure flexibility of choosing VHDCI pins in the serial expansion board, I see the only economical way is to create pads that can be soldered manually through wires.
- Vswt (Unregulated 5V) will be used to power the line-drivers and GPIO header. There will be a fusible resistor to protect the board from overcurrent.
- GPIO header will use an 8-bit bidirectional logic level translator. (Looking for cheapest part that does the job right)
- GPIO header will be 10 pin and will include Ground and 5V supply.
- ESD protectors chosen: GSOT05C (5 will be used near the VHDCI connector)
- Final schematics should be available in 1 or 2 days
- Tried implementing HDMI2USB (master) on Xilinx ISE 14.7 - takes 15 min from synthesize to bitstream on Ubuntu 14.04 LTS (64-bit) and 30 min on my Windows XP (32-bit) VM. My machine has an i5-2520M and 8GB RAM.
- Started reading material on http://www.asic-world.com/vhdl/
Cypress FX2LP:-From my reading I found that the Cypress chip uses the GPIF interface to send bitstreams to the FPGA during programming mode and uses the endpoint buffers called Slave FIFOs to communicate during normal operation of the device. My concern was mainly to check if the FPGA can access these additional endpoints that I would create and that’s indeed possible by accessing the respective FIFOs in the Cypress chip.
This can be seen in usb_top.vhd:
constant cdcout : std_logic_vector(1 downto 0):= "00"; --ep 2
constant cdcin : std_logic_vector(1 downto 0):= "01"; --ep 4
constant uvcin : std_logic_vector(1 downto 0):= "10"; --ep 6
So the task of adding more CDC ACM devices would involve:
· Changing the USB descriptors to describe new interfaces for new CDC ACM devices and their endpoints
· Interfacing the new endpoints to GPIOs in usb_top.vhd
- Revisiting the following diagram (from my proposal) shows a little bit about how the FX2LP is seen as endpoint buffers by the FPGA:
- Just installed their SDK, going through their docs
- Decided on implementing just 2 extra serial ports for now. Procedure for adding more will be documented. Adding more ports dynamically will not be provided in run-time for now.
- Wondering about the driver signing issues I might have in Windows for the custom INFs I will be creating.
Things for coming week:
- Complete the PCB and generate gerber! Will order once we agree on it.
- Look deeper into FX2LP
- Continue my FPGA tutorials